The memory cells of DRAMs are comprised of two main components: a field-effect transistor (FET) and a capacitor. In DRAM cells utilizing a conventional planar capacitor, far more chip surface area is dedicated to the planar capacitor than to the FET. In constructing such a DRAM cell, wordlines are generally etched from a polysilicon-1 layer. A doped region of silicon substrate functions as the lower (storage-node) capacitor plate, while a polysilicon-2 generally functions as the upper capacitor plate (cell plate).
Although planar capacitors have generally proven adequate for use in DRAM chips up to the 1-megabit level, they are considered to be unusable for more advanced DRAM generations. As component density in memory chips has increased, the shrinkage of cell capacitor size has resulted in a number of problems. Firstly, the alpha-particle component of normal background radiation can generate hole-electron pairs in the silicon substrate, which functions as the lower capacitor plate. This phenomena will cause a charge stored within the affected cell capacitor to rapidly dissipate, resulting in a "soft" error. Secondly, the sense amplifier differential signal is reduced. This aggravates noise sensitivity and makes it more difficult to design a sense amplifier having appropriate signal selectivity. Thirdly, as cell capacitor size is decreased, the cell refresh time must generally be shortened, thus requiring more frequent interruptions for refresh overhead The difficult goal of a DRAM designer is therefor to increase or, at least, maintain cell capacitance as cell size shrinks, without resorting to processes that reduce product yield or that markedly increase the number of masking and deposition steps in the production process.
Many manufacturers of 4-megabit DRAMs are utilizing cell designs based on nonplanar capacitors. Two basic capacitor designs are currently in use: the trench capacitor and the stacked capacitor. Both types of nonplanar capacitors typically require a considerable greater number of masking, deposition and etching steps for their manufacture than does a planar capacitor.
In a trench capacitor, charge is stored primarily vertically, as opposed to horizontally in a planar capacitor. Since trench capacitors are fabricated in trenches which are etched in the substrate, the typical trench capacitor, like the planar capacitor, is subject to soft errors. In addition, there are several other problems inherent in the trench design. One problem is that of trench-to-trench charge leakage, caused by the parasitic transistor effect between adjacent trenches. Another problem is the difficulty of completely cleaning the trenches during the fabrication process; failure to completely clean a trench will generally result in a defective cell.
The stacked capacitor design, on the other hand, has proven somewhat more reliable and easier to fabricate than the trench design. Since both the lower and the upper plates of a typical stacked capacitor are formed from individual polysilicon layers, the stacked capacitor is generally much less susceptible to soft errors than either the planar or trench capacitors. By placing both the wordline and the digit line beneath the capacitive layers, and having the lower layer make contact with the substrate by means of a buried contact, some manufacturers have created stacked capacitor designs in which vertical portions of the capacitor contribute significantly to the total charge storing capacity. Since a stacked capacitor generally covers not only the entire area of a cell (including the cell's access FET), but adjacent field oxide regions as well, capacitance is considerably enhanced over that available from a planar type cell. On the negative side, processing steps are complex since correct alignment of the lower capacitor plate to the substrate contact area is critical. It is also difficult to maximize the amount of contact between the lower capacitor plate and the substrate contact area.
Although the stacked cell capacitor is generally considered by many experts to be the wisest choice for the 4-megabit generation, trenches are generally considered to be the best choice for the 16-megabit generation and beyond, due to the fact that trenches can be made deeper for increased capacitance without affecting topography of the array.